arty - MicroBlaze入门

本指南将在步骤步骤中，通过为ARTY FPGA板的Vivado IP Integrator创建基于MicroBlaze的硬件设计。

At the end of this tutorial you will have:

• 在Xilinx Vivado中创建了基于微哔的硬件（HW）设计

• 在Xilinx Vivado SDK（软件开发套件）中创建的.c项目通过硬件设计显示Hello World。

• 最终的输出显示在SDK控制台and Tera Term

Microblaze is a soft IP core from Xilinx that will implement a microprocessor entirely within the Xilinx FPGA general purpose memory and logic fabric. For this tutorial, we are going to add a Microblaze IP block using the Vivado IP Integrator tool.

除了MicroBlaze IP块之外，我们还希望在arty上使用DDR3 SDRAM组件。因此，MIG（内存接口发生器）IP块将被添加到我们的设计中。

Finally, a UART ( universal asynchronous receiver/transmitter ) IP block will be added to communicate between the host PC and the soft processor core running on the Arty.

I. Vivado

• Open Vivado and select Arty board
• 创建一个新的Vivado项目
• Create empty block design workspace inside the new project
• Add required IP blocks using the IP integrator tool and build Hardware Design
• 验证和保存块设计
• Create HDL system wrapper
• 运行设计综合和实施
• Generate Bit File
• Export Hardware Design including the generated bit stream file to SDK tool
• 推出SDK.

现在硬件设计将导出到SDK工具。Vivado到SDK切掉的内部通过Vivado内部完成。我们将使用SDK创建一个软件应用程序，该应用程序将通过从Vivado导入硬件设计信息来使用自定义的电路板接口数据和FPGA硬件配置。

II。SDK.

• Create new application project and select default Hello World template
• 计划FPGA.
• Run configuration by selecting the correct UART COM Port and Baud Rate

• Familiarity with Vivado
• Block Design Experience

• Digilent Arty FPGA Board
• Micro USB Cable
  • Used for UART communication, JTAG programming, and Power

• Xilinx Vivado 2015.4 with the SDK package.
  • Newer versions of Vivado may also work
• Digilent Board Support Files
  • Follow thewiki guideon how to install Board Support Files for Vivado 2015.X

1.1）打开Vivado并点击创建新项目打开Vivado的新项目向导。

1.2）新窗口将打开，单击下一个并且你会看到下面的屏幕。为您的项目命名（没有空格！）并在单击之前选择项目保存目录下一个。Underscores are a good substitute for empty spaces.

1.3）我们将从地下构建这个项目并添加我们自己的来源，以便我们想要创建RTL项目。选择RTL项目并确保此时不要指定来源box is checked. Click下一个。

1.4）如果您遵循了董事会支持文件Wiki指南，则选择木板s。The filter options can be used to quickly find the Arty board, by selecting “digilentinc.com” for Vendor, and “Arty” for Display Name.Artyshould be displayed in the selection list. Selecting a different board name will cause errors later. Click下一个。

1.5）显示新项目设计来源和目标设备的摘要。点击Finish。

At this point you have successfully created a project that will properly communicate with the Arty.

This is the main project window where you can create a IP based block design or add RTL based design sources. The flow navigator panel on the left provides multiple options on how to create a hardware design, perform simulation, run synthesis and implementation and generate a bit file. You can also program the board directly from Vivado with the generated bit file for an RTL project using the Hardware Manager.

For our design, we will use the IP Integrator to create a new block design.

2.1) On the left you should see the Flow Navigator. Select创建块设计在IP集成商下。给您的设计名称（没有任何空的空格）并单击OK。



You have created a new block design.

3.1) Click the木板tab (Highlighted in orange below)



此列表包含在您之前安装的电路板文件中定义的所有组件。这些已经配置为使用几个Vivado IP。

3.2) Click and drag theSystem Clock组件到空块设计上。Vivado will automatically connect this system clock to a new Clocking Wizard block.

3.3）双击Clocking Wizard块定制它。点击一下输出时钟tab and changeclk_out1“166.667”MHz。使能够clk_out2and set it to “200.0”MHz。Set the重置类型toActive Low



点击OK关闭此窗口。

3.4) Click and drag theDDR3 SDRAM.组件到空块设计上。Vivado将自动将DDR3 SDRAM和一些虚拟时钟端口连接到MIG IP。

3.5)删除theclk_ref_iandsys_clk_iports by clicking them and pressing the删除key, or by right clicking them and selecting删除。

3.6）连接clk_out1tosys_clk_ion the MIG block. Connectclk_out2toclk_ref_i。

3.7) ClickRun Connection Automationin the green banner above. The default settings are fine, so clickOK。



Vivado将系统将系统重置为MIG上的sys_rst。连接this new reset port to theresetn在时钟向导块上输入。

4.1) Click the Add IPbutton and search forMicroblaze。



Double clickMicroblazeto add it to your block design.

4.2) ClickRun Block Automation为微孔处理器打开块自动化。

Here you can choose how much memory to give your Microblaze processor.Configure the optionsto match the picture below, then clickOK。确保that you set the Clock Connection to/mig_7series_0/ui_clk。

4.3）运行块自动化将自动生成一组附加IP块，这将根据上一步中选择的选项自动添加到我们的硬件设计中。Do Notclick onRun Connection Automationyet.

5.1）进入木板s再次标签并找到USB UARTcomponent.点击and drag这在块设计上将UartLite块添加到您的设计中。

5.2）点击Run Connection Automation在绿色横幅。检查All Automation复选框并单击OK。



This will create one AXI Interconnect for the DDR Memory and another for peripheral components.
点击the 重新制定布局button to rearrange your block design.

6.1) Select Validate Design。This will check for design and connection errors.

6.2) After the design validation step we will proceed with creating a HDL System Wrapper. Click on the来源tab and find your block design.



Right click on your block design and clickCreate HDL Wrapper。确保Let Vivado manage wrapper and auto-updateis selected and clickOK。



This will create a top module in Verilog and will allow you to generate a bitstream.

7.1）在Vivado的顶部工具栏中，单击 Generate Bitstream。This can also be found in theFlow Navigatorpanel on the left, under计划和调试。
If you haven't already saved your design, you will get a prompt to save the block design.

7.2) The bit file generation will begin. The tool will run合成and执行。合成和实现已成功完成后，将创建位文件。您将在项目窗口的右上角找到综合和实现的状态栏。

This process can take anywhere from2到20分钟根据您的计算机。

7.3) After the bitstream has been generated, a message prompt will pop-up on the screen. You don't have to open the Implemented Design for this demo. Just click取消。

8.1) On the main toolbar, clickFileand select导出→导出硬件。检查box toInclude Bitstream然后点击OK。This will export the hardware design with system wrapper for the Software Development Tool - Vivado SDK.



A new file directory will be created underHello_World.SDK类似于Vivado硬件设计项目名称。另外两个文件，。sysdefand。hdf也创造了。这一步基本上creates a new SDK Workspace.

8.2）在主工具栏上，单击File然后推出SDK.。Leave both of the dropdown menus as their default本地项目然后点击OK。This will open Xilinx SDK and import your hardware.

9.1) The HW design specification and included IP blocks are displayed in thesystem.hdf.文件。Xilinx SDK独立于Vivado，即，从这一点开始，您可以在导出的HW设计顶部的C / C ++中创建SW项目。如有必要，您还可以直接从主Vivado项目目录中创建的SDK文件夹启动SDK。

From this point, if you need to go back to Vivado and make changes to the HW design, then it is recommended to close the SDK window and make the required HW design edits in Vivado. After this you must follow the sequence of creating a new HDL wrapper, save design and bit file generation. This new bit file and system wrapper must then be exported to SDK.

9.2）内项目资源管理器左侧选项卡，您可以看到您的硬件平台。

系统is the name of your block design created in Vivado. This hardware platform has all the HW design definitions, IP interfaces that have been added, external output signal information and local memory address information.

10.1) Click the Newdropdown arrow and selectXilinx→应用程序项目。



为您的项目提供一个没有空空格的名称，然后单击下一个。

10.2) SelectHello World从模板列表中，单击Finish。

您将看到两个新文件夹项目资源管理器panel.

• Hello_worldwhich contains all the binaries, .C and .H (Header) files
• hello_world_bsp.which is the board support folder

Hello_worldis our main working source folder. This also contains an important file shown here which is the “lscript.ld”. This is a Xilinx auto generated linker script file. Double click on this file to open.

10.3）回到项目资源管理器, double click and openhelloworld.cunder thesrc文件夹。

这是主要的.c文件，在执行时将在控制台中打印“Hello World”。

11.1) Make sure that the Arty is turned on and connected to the host PC via the USB-JTAG port - this port will serve dual purpose as the USB-UART connection to the Microblaze.

On the top toolbar, click the 计划FPGA.button.

11.2）点击Program使用硬件设计编程FPGA。

12.1）打开串行终端应用程序（TERA术语）。连接到具有9600的波特率的arty UART端口。通过双击UartLite块，可以通过双击块设计中的这种波特率进行更改。

13.1）回到SDK中，选择您的Hello_world项目并单击 Run As…button. SelectLaunch on Hardware (System Debugger)然后点击OK。

13.2）您的程序将运行，您应该看到串行终端内部的“Hello World”弹出。h