Genesys 2 - Getting Started with Microblaze

本指南将提供使用Venesys2 FPGA板的Vivado IP集成器创建基于微蓝光的硬件设计的逐步演练。NOTE: The Genesys2 requires Vivado Design Edition or System Edition which supports the Kintex-7 FPGA

Microblaze is a soft IP core from Xilinx that will implement a microprocessor entirely within the Xilinx FPGA general purpose memory and logic fabric. For this tutorial, we are going to add a Microblaze IP block using the Vivado IP Integrator tool.

In addition to the Microblaze IP block, we would also like to make use of the DDR3 SDRAM component on the Genesys2. Therefore a MIG ( Memory Interface Generator ) IP block will be added to our design.

Finally, a UART ( universal asynchronous receiver/transmitter ) IP block will be added to communicate between the host PC and the soft processor core running on the Genesys2.

I. Vivado

• Open Vivado and select Genesys2 board
• Create an new Vivado Project
• 在新项目中创建空块设计工作区
• Add required IP blocks using the IP integrator tool and build Hardware Design
• Validate and save block design
• Create HDL system wrapper
• Run design Synthesis and Implementation
• 生成位文件
• Export Hardware Design including the generated bit stream file to SDK tool
• Launch SDK

现在的硬件设计是导出SDKl. The Vivado to SDK hand-off is done internally through Vivado. We will use SDK to create a Software application that will use the customized board interface data and FPGA hardware configuration by importing the hardware design information from Vivado.

II. SDK

• Create new application project and select default Hello World template
• Program FPGA
• Run configuration by selecting the correct UART COM Port and Baud Rate

• Digilent Genesys2 FPGA Board
• 2个微型USB电缆
  • For both UART communication and JTAG programming

• Xilinx Vivado 2015.X
  • 必须安装系统版或设计版本以支持Kintex-7 FPGA
• Xilinx SDK
  • Same version as your vivado installation
• Serial Terminal Application
  • Tera Term is used in this tutorial

• Genesys 2 Support Files
  • These files will describeGPIOinterfaces on your board and make it easier to select your FPGA board and addGPIOIP blocks
  • Follow this Wiki guideVivado Board Files for Digilent 7-Series FPGA Boardson how to install Board Support Files for Vivado 2015.X

当您第一次运行Vivado时，这将是您可以创建新项目或打开最近一个项目的主要开始窗口。

1.1) Click onCreate New Project。Choose the Project Name and Location such that there areno blank spaces。This is an important naming convention to follow for project names, file names and location paths.
Underscore in a good substitute for empty spaces.

It is good practice to have a dedicated folder for Vivado Projects, preferably with the smallest possible path length. Example: C:/Vivado_Projects.

Name your Project and select the Project location and clickNext。

1.2) Choose Project Type asRTL项目。留下 - 不要指定未选中的来源框，然后单击Next。

1.3）我们不会在这里导入或创建任何文件，因此请单击Next直到部分选择屏幕。

1.4) If you have completed theBoard Support File Wiki guide, selectBoards。
Genesys2 should be displayed in the selection list. A mismatch in selecting the correct board name will cause errors. Select theGenesys2和clickNext。

1.5) A summary of the new project design sources and target device is displayed. Click结束。

This is the main project window where you can create a IP based block design or add RTL based design sources. The flow navigator panel on the left provides multiple options on how to create a hardware design, perform simulation, run synthesis and implementation and generate a bit file. You can also program the board directly from Vivado with the generated bit file for an RTL project using the Hardware Manager.

For our design, we will use the IP Integrator to create a new block design.

2.1) On the left you should see the Flow Navigator. SelectCreate Block Designunder the IP Integrator. Give a name to your design (without any empty spaces) and click好的。



您已经创建了一个新的块设计。

3.1) Click theBoardtab (Highlighted in orange below)



This list contains all of the components defined in the board file you installed before. These are already configured to work with several Vivado IPs.

3.2) Click and drag theDDR3 SDRAM组件到空块设计。Vivado将自动将DDR3 SDRAM和系统时钟连接到MIG IP。

3.3) Click运行连接自动化in the green banner above. Click好的。



Vivado will connect your system reset to sys_rst on the MIG.

4.1) Click the 添加IP按钮并搜索Microblaze。



Double clickMicroblazeto add it to your block design.

4.2) ClickRun Block Automationto open the Block automation for the Microblaze processor.

在这里，您可以选择多少内存来给您的微封红线处理器。Configure the optionsto match the picture below, then click好的。

4.3) Running the block automation will auto-generate a set of additional IP blocks which will be added to our hardware design automatically based on the options selected in the previous step.Do not click on Run Connection Automation yet.

5.1) Go into theBoardstab again and find theUSB UARTcomponent.Click and dragthis onto the block design to add the Uartlite block to your design.

5.2) Click运行连接自动化in the green banner. Check theAll Automationcheckbox and click好的。



这将为DDR存储器创建一个AXI互连，另一个用于外围组件。
Click the Regenerate Layout按钮重新排列您的块设计。

6.1）选择 Validate Design。This will check for design and connection errors.

6.2）在设计验证步骤之后，我们将继续创建HDL系统包装器。单击Sourcestab and find your block design.



Right click on your block design and click创建HDL包装器。Let Vivado manage wrapper and auto-update和click好的。



This will create a top module in VHDL and will allow you to generate a bitstream.

7.1) In the top toolbar in Vivado, click 生成bitstream。This can also be found in theFlow Navigatorpanel on the left, underProgram and Debug。
If you haven't already saved your design, you will get a prompt to save the block design.

7.2) The bit file generation will begin. The tool will runSynthesis和Implementation。After both synthesis and implementation have been successfully completed, the bit file will be created. You will find a status bar of Synthesis and Implementation running on the top right corner of the project window.

这个过程可能需要2 to 20 minutesdepending on your computer.

7.3) After the bitstream has been generated, a message prompt will pop-up on the screen. You don't have to open the Implemented Design for this demo. Just clickCancel。

8.1) On the main toolbar, click文件和selectExport Hardware。Check the box toInclude Bitstream和click好的。This will export the hardware design with system wrapper for the Software Development Tool - Vivado SDK.



将在下面创建一个新的文件目录Hello_World.SDKsimilar to the Vivado hardware design project name. Two other files,.sysdef和.hdf也创造了。这个步骤创建一个new SDK Workspace.

8.2) On the main toolbar, click文件和thenLaunch SDK。将两个下拉菜单作为默认Local to Project和click好的。This will open Xilinx SDK and import your hardware.

9.1）HW设计规范和随附的IP块显示在system.hdffile. Xilinx SDK is independent of Vivado, i.e. from this point, you can create your SW project in C/C++ on top of the exported HW design. If necessary, you can also launch SDK directly from the SDK folder created in the main Vivado Project directory.

From this point, if you need to go back to Vivado and make changes to the HW design, then it is recommended to close the SDK window and make the required HW design edits in Vivado. After this you must follow the sequence of creating a new HDL wrapper, save design and bit file generation. This new bit file and system wrapper must then be exported to SDK.

9.2) Within theProject Explorertab on the left, you can see your hardware platform.

systemis the name of your block design created in Vivado. This hardware platform has all the HW design definitions, IP interfaces that have been added, external output signal information and local memory address information.

10.1) Click the Newdropdown arrow and select申请项目。



Give your project a name that has no empty spaces and clickNext。

10.2）选择Hello Worldfrom the list of templates and click好的。

You will see two new folders in theProject Explorerpanel.

• display_hello_worldwhich contains all the binaries, .C and .H (Header) files
• display_hello_world_bspwhich is the board support folder

display_hello_world是我们的主要工作源文件夹。这还包含这里显示的重要文件，即“ lscript.ld”。这是Xilinx自动生成的链接脚本文件。双击此文件以打开。

10.3) Back in theProject Explorer, double click and openhelloworld.cunder thesrcfolder.

This is the main .C file which will printhello worldin the console when executed.

11.1) Make sure that the Genesys2 is turned on and connected to the host PC via both theJTAGUSB port和theuartUSB port.

On the top toolbar, click the Program FPGAbutton.

11.2) ClickProgramto program your FPGA with your hardware design.

12.1) Open up a Serial Terminal application (Tera Term). Connect to the Genesys2 UART port with a baud rate of 9600. This baud rate can be altered in your block design by double clicking the Uartlite block.

13.1) Back in SDK, select yourHello_worldproject and click the Run As…button. SelectLaunch on Hardware (System Debugger)和click好的。

13.2）您的程序将运行，您应该看到Hello Worldpop up inside of your Serial Terminal.