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联合测试动作组（JTAG）-SMT2是用于Xilinx现场可编程栅极阵列（FPGAS）的紧凑，完整且完全独立的表面编程模块。可以直接从所有Xilinx工具中访问该模块，包括Impact，Chipscope，Efuse，Vivado和Edk。用户可以将模块直接加载到目标板上，并像其他任何组件一样对其进行重新流动。

The JTAG-SMT2 uses a 3.3V main power supply and a separate Vref supply to drive the JTAG signals. All JTAG signals use high speed, 24mA, three-state buffers that allow signal voltages from 1.8V to 5V and bus speeds of up to 30MBit/sec. The JTAG bus can be shared with other devices as systems hold JTAG signals at high-impedance, except when actively driven during programming. The SMT2 module is CE certified and fully compliant with EU RoHS and REACH directives. The module uses a standard Type-A to Micro-USB cable available for purchase from Digilent, Inc.

• Small, complete, all-in-one JTAG programming/debugging solution for Xilinx FPGAs
• Compatible with all Xilinx tools
• Compatible with IEEE 1149.7-2009 Class T0 – Class T4 (includes 2-Wire JTAG)
• GPIOpin allows debugging software to reset the processor core of Xilinx’s Zynq platform
• 单个3.3V电源
• Separate Vref drives JTAG signal voltages; Vref can be any voltage between 1.8V and 5V.
• High-Speed USB2 port that can drive JTAG/SPI bus at up to 30Mbit/sec (frequency settable by user)
• SPI programming solution (modes 0 and 2 up to 30Mbit/sec, modes 1 and 3 up to 2Mbit/sec)
• 使用Micro-AB USB2连接器
• 小因素的表面安装模块可以直接加载到目标板上
• 类似的电路作为独立编程电缆也可以使用。参见Digilent的JTAG-HS2。

用户可以将JTAG信号直接连接到相应的FPGA信号，如图1所示。为了获得最佳结果，将模块安装在主机PCB边缘上的模块上。尽管用户可能会在SMT2下方的主机PCB顶部运行信号轨迹，但Digilent建议将该区域立即在SMT2下方保持清晰。注意：将SMT2和FPGA之间的阻抗保持在100欧姆以下，以最大的速度操作JTAG。SMT2通过添加了三个通用IO引脚（GPIO0 - GPIO2），并在2个和4线模式下添加了IEEE 1149.7-2009 JTAG目标，从而改善了SMT2。

In addition to supporting JTAG, the JTAG-SMT2 also features eight highly configurable Serial Peripheral Interface (SPI) ports that allow communication with virtually any SPI peripheral. (See figure 2) All eight SPI ports share the same SCK,莫西, and味噌引脚，因此用户可以在任何给定时间仅启用一个端口。图3中的表总结了每个端口支持的功能。HS2支持SPI模式0、1、2和3。

注意:Xilinx工具s expect GPIO2/CS3 to be connected to the SRST_B pin on a Zynq chip. As a result, SPI ports 6 and 7 may not be used for SPI communication if the Xilinx tools are going to be used to communicate with the SMT2.

In addition to working seamlessly with all Xilinx tools,which includes iMPACT, Chipscope, eFuse, Vivado and EDK. Digilent’s Adept software and the Adept software development kit (SDK) support the SMT2 module. For added convenience customers may freely downloaded the SDK from Digilent’s website. This Adept software includes a full-featured programming environment and a set of public application programming interfaces (API) that allow user applications to directly drive the JTAG chain.

With the Adept SDK users can create custom applications that will drive JTAG ports on virtually any device. Users may utilize the API’s provided by the SDK to create applications that can drive any SPI device supporting those modes. Please see the Adept SDK reference manual for more information.

JTAG-HS2支持多种扫描格式，包括JSCAN0-JSCAN3，MSCAN和OSCAN0-OSCAN7。它能够在由T0 - T4 JTAG目标系统（TS）组成的4线和2线扫描链中进行通信。（见图4和5）

IEEE 1149.7-2009规范需要任何功能充当调试和测试系统（DTS）的设备，以在TMS和TDO引脚上提供上拉偏置。为了满足此要求，JTAG-SMT2在TMS，TDI，TDO和TCK信号上具有弱上拉（100K欧姆）。尽管规格不需要，但TDI和TCK信号上的上拉值确保没有信号在其他源没有驱动它们时浮动。（见图6）

Users should place a current limiting resistor between the TMS pin of the SMT2 and the TMSC pin of the TS when using the JTAG-SMT2 to interface with an 1149.7 compatible TS. If a drive conflict occurs, this resistor should prevent damage to components by limiting the amount of current flowing between the pins of each device. A 200ohm resistor will limit the maximum current to 16.5mA when using a 3.3V reference. (See Figure 7 & 8) While this level of resistance should be sufficient for most applications, the value of the resistor may need to be adjusted to meet the requirements of the TS.

In most cases users can avoid a drive conflict by having applications that use the SMT2 communicate with the TS in two wire mode. Use the applications to reconfigure the TS to use the JScan0, JScan1, JScan2, or JScan3 scan format prior to disabling the SMT2’s JTAG port.

The Adept SDK provides an example application that demonstrates how to communicate with a Class T4 TAP controller using the MScan, OScan0, and OScan1 scan formats.

The JTAG-SMT2 has three general purpose IO pins (GPIO0, GPIO1, and GPIO2) that are useful for a variety of different applications. Each pin features high speed three-state input and output buffers. At power up the JTAG-SMT2 disables these output buffers and places the signals in a high-impedance state. Each signal remains in a high-impedance state until a host application enables DPIO port 0 and configures the applicable pin as an output. When the host application disables DPIO port 0 allGPIO引脚恢复到高阻抗状态。弱上拉（100k欧姆）确保GPIO信号不会浮动而不是交流tively driven. (See figure 9)

When customers use the JTAG-SMT2 to interface the scan chain of Xilinx’s Zynq platform, they should connect the GPIO2 pin of the SMT2 to the Zynq’s PS_SRST_B pin. This connection allows the Xilinx Tools to reset the Zynq’s processor core at various times during debugging operations. Please see the following “Application Examples” section for more information.注意:Xilinx工具s expect GPIO2 to be connected to the SRST_B pin on a Zynq chip. As a result, GPIO2 may not be used as a general purpose I/O if the Xilinx tools are going to be used to communicate with the SMT2. Note: DPIO port 0 can only be used while both JTAG and SPI are disabled.

示例1: Interfacing a Zynq-7000 when VCCO_0 and VCCO_MIO1 use a common supply

Figure 10 demonstrates how to connect the JTAG-SMT2 to Xilinx’s Zynq-7000 silicon when the same voltage supplies both the VCCO_0 (Programmable Logic Bank 0 Power Supply) and the VCCO_MIO1 (Processor MIO Bank 1 Power Supply). In this case the SMT2 has a 100K pull-up to VREF, which operates at the same voltage as VCCO_MIO1. This similar voltage makes it possible to eliminate the external pull-up that is normally required for the PS_SRST_B pin.

示例2：接口使用不同电压的Zynq-7000用于VCCO_0和VCCO_MIO1

图11演示了如何将JTAG-SMT2连接到Xilinx的Zynq-7000硅时，当不同电压提供VCCO_0（可编程逻辑库0电源）和VCCO_MIO1（处理器Mio Bank 1电源）。如果Zynq的JTAG引脚与PS_SRST_B的电压不同，则需要外部缓冲区来调整GPIO2信号的水平。图10中的示例演示了使用开放排水缓冲区的使用，以允许添加重置按钮。

示例3: Interfacing a Zynq-7000 while retaining the Xilinx JTAG Header

Figure 12 below demonstrates how to connect the JTAG-SMT2 to Xilinx’s Zynq-7000 silicon alongside Xilinx’s 14-pin JTAG header. In this example the open drain buffers allow both the SMT2 and Xilinx JTAG Header to drive the PS_SRST_B pin, which may operate a different voltage than the Zynq’s JTAG pins.

JTAG-SMT2能够针对以下Xilinx设备：

1. Xilinx FPGAs, including UltraScale+
2. Xilinx SoCs, MPSoCs, and RFSoCs, including Xilinx Zynq-7000 and Zynq UltraScale+
3. Xilinx ACAPs, including Versal

• xilinx coolrunner™/coolrunner-ii cplds
• Xilinx Platform Flash ISP configuration PROMs
• Select third-party SPI PROMs
• Select third-party BPI PROMs

JTAG-SMT2不能针对以下设备：

• Xilinx 9500/9500XL CPLDs
• Xilinx 1700 and 18V00 ISP configuration PROMs
• xilinx fpga fpga编程

与Xilinx的Impact软件一起使用时，JTAG-SMT2不支持远程设备配置。注意：请参阅“间接编程简介 - SPI或BPI闪存”的帮助主题，以了解支持的FPGA/PROM组合列表。注意：有关Vivado支持的FPGA/PROM组合列表，请参见Xilinx UG908的“配置内存支持”部分。

Note: PCB dimensions have a tolerance of +/- 0.13mm.

Measurements are in mm

The JTAG-SMT2’s JTAG signals operate according to the timing diagram in figure 13. The SMT2 supports JTAG/TCK frequencies from 30MHz to 8KHz at integer divisions of 30MHz from 1 to 3750. Common frequencies include 30MHz, 15MHz, 10Mhz, 7.5MHz, and 6MHz. (See table in figure 14) The JTAG/TCK operating frequency can be set within the Xilinx tools.Note: Please refer to Xilinx’s iMPACT documentation for more information.

The JTAG-SMT2 module has a moisture sensitivity level (MSL) of 6. Prior to reflow, the JTAG-SMT2 module must be dried by baking it at 125° C for 17 hours. Once this process has been completed, the module has a MSL of 3 and is suitable for reflow for up to 168 hours without additional drying.

工厂使用2U“ 150U” Electross Nickel使用ENIG工艺完成JTAG-SMT2信号垫。这使得SMT2与大多数安装和回流过程兼容。（见图15）焊料的结合力足以将SMT2牢固地固定在适当的位置，因此安装不需要其他粘合剂。

Digilent ships small quantities of less than 45 per order individually packaged in antistatic bags. Digilent will pack and ship larger quantities in groups of 45 positioned in an antistatic bubble tray. (See figure 16)