5.1) The PmodOLEDrgb requires a 50MHz ext_spi_clk, so we must generate this clock from the MIG (in a Microblaze design) or from the Zynq processor(in a Zynq design).
Microblaze: Double click the mig_7series block to re-customize it. In the Xilinx Memory Interface Generator window, keep clickingNextuntil you seeSelect Additional Clocks(shown below). Click this box and select a 50MHz or less clock from the drop down list.



When finished, keep clickingNext。When you reach the pin selection screen, clickValidateand thenOK。Keep clickingNext。ClickAccepton the license agreement screen, then continue to clickNext。Once you've reached the end, clickGenerateto regenerate your MIG block with your additional clocks.

Zynq:双击ZYNQblock to re-customize it. In the menu to the left, clickClock Configuration。打开PL Fabric Clocksdrop down and check the next free FCLK_CLK and set the requested frequency to 50MHz or less. ClickOK。

5.2) Connect this new clock to theext_spi_clkinput on the PmodOLEDrgb block.