Genesys 2 - Getting Started with Microblaze Servers

Note:The Genesys2 uses a Gigabit Ethernet module which requires the TEMAC IP that isnot contained in the Vivado Webpack。为了完成本教程之后,您必须either purchase a license for the TEMAC IP or get the evaluation license for free from their website by followingthis guide。

This guide will provide a step by step walk-through of creating a Microblaze based hardware design using the Vivado IP Integrator that will build over theGetting Started with Microblazeguide by making use of the on-board Ethernet port and GPIOs for the Genesys2 FPGA board.

At the end of this tutorial you will have a comprehensive hardware design for the Genesys2 that makes use of various Hardware ports on the Genesys2 which are managed by the Microblaze Softcore Processor block.

NOTE: The Genesys2 requires Vivado Design Edition or System Edition which supports the Kintex-7 FPGA. This is not the same as the free webpack version

Important:This guide only officially supports Vivado and Xilinx SDK 2015.4. Differences in IP and drivers between different versions of the tools make it so that while the steps presented here may be useful in other versions, unforeseen issues may arise. Proceed at your own risk.

• Digilent Genesys2 FPGA Board
• 2 Micro USB Cables for UART communication and JTAG programming
• Ethernet Cable

• Xilinx Vivado 2015.X
  • System Edition or Design Edition must be installed to support the Kintex-7 FPGA
• Xilinx SDK
  • Same version as your Vivado installation
• Serial Terminal Application
  • Tera Term is used in this tutorial
• TEMAC IP license installed
  • Follow this Wiki guide:Installing the 120 Day Evaluation License for the TEMAC IP。

• Board Support Files– These files will describeGPIOinterfaces on your board and make it easier to select your FPGA board and addGPIOIP blocks.
  • Follow this Wiki guideVivado Board Files for Digilent 7-Series FPGA Boardson how to install Board Support Files for Vivado 2015.X

When you first run Vivado this will be the main start window where you can create a new project or open a recent one.

1.1) Click onCreate New Project。Choose the Project Name and Location such that there areno blank spaces。This is an important naming convention to follow for project names, file names and location paths.
Underscore in a good substitute for empty spaces.

It is good practice to have a dedicated folder for Vivado Projects, preferably with the smallest possible path length. Example: C:/Vivado_Projects.

Name your Project and select the Project location and clickNext。

1.2) Choose Project Type asRTL Project。Leave the - do not specify sources box unchecked and clickNext。

1.3) We will not be importing or creating any files here, so clickNextuntil the part select screen.

1.4) If you have completed theBoard Support File Wiki guide, selectBoards。
Genesys2 should be displayed in the selection list. A mismatch in selecting the correct board name will cause errors. Select theGenesys2and clickNext。

1.5) A summary of the new project design sources and target device is displayed. ClickFinish。

This is the main project window where you can create a IP based block design or add RTL based design sources. The flow navigator panel on the left provides multiple options on how to create a hardware design, perform simulation, run synthesis and implementation and generate a bit file. You can also program the board directly from Vivado with the generated bit file for an RTL project using the Hardware Manager.

For our design, we will use the IP Integrator to create a new block design.

2.1) On the left you should see the Flow Navigator. SelectCreate Block Designunder the IP Integrator. Give a name to your design (without any empty spaces) and clickOk。



You have created a new block design.

3.1) Click theBoardtab (Highlighted in orange below)



This list contains all of the components defined in the board file you installed before. These are already configured to work with several Vivado IPs.

3.2) Click and drag theDDR3 SDRAMcomponent onto the empty block design. Vivado will automatically connect the DDR3 SDRAM and system clock to the MIG IP.

3.3) ClickRun Connection Automationin the green banner above. ClickOk。



Vivado will connect your system reset to sys_rst on the MIG.

4.1) Click the Add IPbutton and search forMicroblaze。



Double clickMicroblazeto add it to your block design.

4.2) ClickRun Block Automationto open the Block automation for the Microblaze processor.

Here you can choose how much memory to give your Microblaze processor.Configure the optionsto match the picture below, then clickOK。

4.3) Running the block automation will auto-generate a set of additional IP blocks which will be added to our hardware design automatically based on the options selected in the previous step.Do not click on Run Connection Automation yet.

5.1) Go into theBoardstab again and find theUSB UARTcomponent.Click and dragthis onto the block design to add the Uartlite block to your design.

5.2) Find theEthernet PHYanddrag this onto the block designto add the Ethernet block to your design.

5.3) Click the Add IPbutton and search forTimer。Double clickAXI Timerto add it to your block design.

5.4) ClickRun Block Automationin the green banner. Then clickOKon the screen that pops up.



This will create a new Ethernet DMA IP block as well as a clock wizard.

5.5) Find the clock wizardaxi_ethernet_0_refclkand connectclk_in1to theui_clkoutput on themig_7series_0block.

5.6) ClickRun Connection Automationin the green banner. Check theAll Automationcheckbox and clickOK。



You might get a warning about obsolete automations. JustRun Connection Automation再次对所有自动化。这将创建一个阿喜Interconnect for the DDR Memory and another for peripheral components.

6.1) Find theConcatblock and double click it to open its settings.

6.2) Change theNumber of Portsto5。ClickOK。

6.3) The Concat block takes interrupt inputs and sends them to the Microblaze controller.



Route the following connections to the inputs of theConcatblock; order does not matter:
-interrupton theAXI Timerblock.
-mm2s_introutands2mm_introuton theaxi_ethernet_0_dmablock.
-mac_irqandinterrupton theaxi_ethernet_0block.

7.1) Click the Regenerate Layoutbutton to rearrange your block design.

7.2) Select Validate Design。This will check for design and connection errors.

7.3) After the design validation step we will proceed with creating a HDL System Wrapper. Click on theSourcestab and find your block design.

7.4) Right click on your block design and clickCreate HDL Wrapper。Let Vivado manage wrapper and auto-updateand clickOK。



This will create a top module in VHDL and will allow you to generate a bitstream.

8.1) In the top toolbar in Vivado, click Generate Bitstream。This can also be found in theFlow Navigatorpanel on the left, underProgram and Debug。
If you haven't already saved your design, you will get a prompt to save the block design.

8.2) The bit file generation will begin. The tool will runSynthesisandImplementation。After both synthesis and implementation have been successfully completed, the bit file will be created. You will find a status bar of Synthesis and Implementation running on the top right corner of the project window.

This process can take anywhere from5 to 60 minutesdepending on your computer.

8.3) After the bitstream has been generated, a message prompt will pop-up on the screen. You don't have to open the Implemented Design for this demo. Just clickCancel。

9.1) On the main toolbar, clickFileand selectExport Hardware。Check the box toInclude Bitstreamand clickOK。This will export the hardware design with system wrapper for the Software Development Tool - Vivado SDK.



A new file directory will be created underecho_server.SDKsimilar to the Vivado hardware design project name. Two other files,。sysdefand。hdfare also created. This step essentially creates a new SDK Workspace.

9.2) On the main toolbar, clickFileand thenLaunch SDK。Leave both of the dropdown menus as their defaultLocal to Projectand clickOK。This will open Xilinx SDK and import your hardware.

10.1) The HW design specification and included IP blocks are displayed in thesystem.hdffile. Xilinx SDK is independent of Vivado, i.e. from this point, you can create your SW project in C/C++ on top of the exported HW design. If necessary, you can also launch SDK directly from the SDK folder created in the main Vivado Project directory.

From this point, if you need to go back to Vivado and make changes to the HW design, then it is recommended to close the SDK window and make the required HW design edits in Vivado. After this you must follow the sequence of creating a new HDL wrapper, save design and bit file generation. This new bit file and system wrapper must then be exported to SDK.

10.2) Within theProject Explorertab on the left, you can see your hardware platform.

systemis the name of your block design created in Vivado. This hardware platform has all the HW design definitions, IP interfaces that have been added, external output signal information and local memory address information.

11.1) Click the Newdropdown arrow and selectApplication Project。



Give your project a name that has no empty spaces and clickNext。

11.2) SelectlwIP Echo Serverfrom the list of templates and clickOK。

You will see two new folders in theProject Explorerpanel.

• echo_server它包含所有的二进制文件,. c和. h(头吗) files
• echo_server_bspwhich is the board support folder

echo_serveris our main working source folder. This also contains an important file shown here which is the “lscript.ld”. This is a Xilinx auto generated linker script file. Double click on this file to open.

11.3) Back in theProject Explorer, double click and opensystem.mssunder theecho_server_bspfolder. ClickModify this BSP's Settings。

11.4) Clicklwip141then findtemac_adapter_optionsand click the arrow. Findphy_link_speedand change the Value toCONFIG_LINKSPEED100。If your router supports Gigabit transfers, change this value toCONFIG_LINKSPEED1000。ClickOK。

12.1) Make sure that the Genesys2 is turned on and connected to the host PC via both theJTAGUSB portandtheUARTUSB port.

On the top toolbar, click the Program FPGAbutton.

12.2) ClickProgramto program your FPGA with your hardware design.

13.1) Open up a Serial Terminal application (Tera Term). Connect to the Genesys2 UART port with a baud rate of 9600. This baud rate can be altered in your block design by double clicking the Uartlite block.

14.1) Make sure you have your Genesys2 plugged into a router before beginning.

14.2) Back in SDK, select yourecho_serverproject and click the Run As…button. SelectLaunch on Hardware (System Debugger)and clickOK。

14.3) Your program will run and you should see the IP information inside of your Serial Terminal.

14.4) Connect to the echo server by opening another terminal and connecting to theBoard IP on port 7。

14.5) Test your echo server by typing something into the terminal. Depending on your settings, you might not see the characters until you pressEnter。When you do, the message will be sent to the Echo Server, and will be echoed back onto your Terminal!