~~TechArticle~~ ====== Add a Zynq Processor to a Block Design ====== //The Zynq7 Processing System IP represents the non-FPGA components of a Zynq chip, referred to as the Processing System, or PS. It must be used in a block design that wants to connect anything to the processor, and to configure PS-side peripherals, clocks, and other settings.// **Note:** //This section only applies to boards with a 7-series Zynq chip.// ---- In the block diagram pane's toolbar, click the **Add IP** button ({{:learn:programmable-logic:tutorials:2020.1:add-zynq-processor:add-ip.png?nolink|}}). ---- <WRAP group> <WRAP column half> In the pop up, search for and double click on **ZYNQ7 Processing System**. </WRAP> <WRAP column half> {{ :learn:programmable-logic:tutorials:2020.1:add-zynq-processor:add-zynq.png?600 |}} </WRAP> </WRAP> ---- <WRAP group> <WRAP column half> Click **Run Block Automation** in the Design Assistance banner (the green bar). </WRAP> <WRAP column half> {{ :learn:programmable-logic:tutorials:2020.1:add-zynq-processor:run-block-automation-1.png?600 |}} </WRAP> </WRAP> ---- <WRAP group> <WRAP column half> In the dialog that pops up, leave all settings as defaults. //Apply Board Preset// should be checked. </WRAP> <WRAP column half> {{ :learn:programmable-logic:tutorials:2020.1:add-zynq-processor:run-block-automation-2.png?600 |}} </WRAP> </WRAP> ---- The needs of your project may require that you change some of the default settings of the Zynq PS. To edit its settings, double click on it to open the configuration wizard. Two specific cases are highlighted below: ---- <WRAP group> <WRAP column half> The Zynq PS can generate multiple clocks that are then provided to the FPGA fabric. These clocks are referred to as FCLKs, and can be found in the **Clock Configuration** tab of the Zynq PS configuration wizard. They are located under the //PL Fabric Clocks// dropdown. They can be enabled (or disabled) with a checkbox, the hardware used to drive the clock can be changed, and the frequency can be modified. All board files for Digilent Zynq boards enable a single Zynq PL clock by default, which is intended to be used with peripherals connected to the Zynq's M_AXI_GP0 port. Some designs may require additional clocks of specific frequencies be added to your design. In these cases, enable a second clock and specify the needed frequency, as seen in the image to the right. **Note:** //This section can always be returned to later, as the addition of an additional clock can be performed any time before the hardware is built.// </WRAP> <WRAP column half> {{ :learn:programmable-logic:tutorials:2020.1:add-zynq-processor:add-additional-clock.png?600 |}} </WRAP> </WRAP> ---- <WRAP group> <WRAP column half> Zynq devices can also use interrupts generated in FPGA fabric to trigger interrupts within the Processing System. Interrupt-related settings can be changed within the configuration wizard's interrupts tab. These interrupts typically use the IRQ_F2P port, which can be found under the Fabric Interrupts -> IRQ_F2P dropdown. To enable this port, both the Fabric Interrupts and IRQ_F2P ports must be enabled. </WRAP> <WRAP column half> {{ :learn:programmable-logic:tutorials:2020.1:add-zynq-processor:add-zynq-interrupt.png?600 |}} </WRAP> </WRAP> ---- <WRAP group> <WRAP column half> While interrupts can be directly connected to the IRQ_F2P port (by clicking and dragging from one port to another), some designs may require multiple interrupt sources. In these cases, add a **Concat** IP to your block design, and manually connect it to the IRQ_F2P port. Additional input ports can be added to a Concat block through its configuration wizard (opened by double clicking on the IP). </WRAP> <WRAP column half> {{ :learn:programmable-logic:tutorials:2020.1:add-zynq-processor:add-zynq-interrupt-concat.png?600 |}} </WRAP> </WRAP>