~~ TechArticle ~~ ========构建Vivado项目=========== <Wrap group> <Wrap列半>此时，Vivado Project可以通过合成和实现来构建Vivado项目，最后生成一个botstream。单击//程序中的**生成bitstream **按钮，并在窗口左侧的// flow navigator // flow navigator // debug //。</wrap> <wrap列半> {{：学习：可编程逻辑：教程：2020.1：生成bitstream：generate-bitstream：generate-bitStream-1.png？600 |}}}} </wrap> </wrap> </wrap> </wrap> --------------------------------------<Wrap Group> <Wrap列Half>将弹出一个对话框，其中包含多个选项，用于如何运行合成和实现。大多数应作为默认值留下。尤其重要的是//工作数//下拉列表，用于指定计算机的资源应专用于构建的多少。大量的工作将专用更多资源，这将使构建得以更快地完成。建议选择最高的可用号码。**注意：** //有关如何安全地忽略其他IP中包含的IP的关键警告。与某些Zynq板上看到的负CK-to-DQS延迟有关的警告也是如此。///取决于设计的复杂性，所使用的板和计算机的强度，构建项目的过程可以采取 between 5 and 60 minutes. </WRAP> <WRAP column half> {{ :learn:programmable-logic:tutorials:2020.1:generate-bitstream:generate-bitstream-2.png?600 |}} </WRAP> </WRAP> ---- <WRAP group> <WRAP column half> When complete, a dialog will pop up that presents several options for what to do next: * //Open Implemented Design// can be used to view the actual hardware design that has been implemented and will be placed onto the chip. * //View Reports// can be used to view additional information about the design, including how much of the resources of the FPGA will be used by the design. * //Open Hardware Manager// can be used to go directly to Vivado's Hardware Manager, which can be used to program a hardware design onto a board. This is typically used for designs that do not involve a software component. * //Generate Memory Configuration File// can be used to create a file for programming an FPGA-only design into flash memory. If none of these options are desired, click **Cancel** to continue. </WRAP> <WRAP column half> {{ :learn:programmable-logic:tutorials:2020.1:generate-bitstream:generate-bitstream-3.png?600 |}} </WRAP> </WRAP> ----